The basis of all micro-fabrication techniques is the replication of a pattern in a substrate. In photolithography, a series of contact masks are used to transfer a series of patterns onto the surface of a microcircuit chip. As each pattern is formed on top of the last, individual circuit elements are built up layer by layer.
Narrow linewidth metal features are advantageously used for etch masks in microcircuit fabrication processes because of the generally higher durability of metal masks in conventional high energy fabrication processes such as plasma etching followed by annealing at high temperature. Narrow linewidth metal features are also independently useful as interconnections for microelectronic and nanoelectronic devices In addition, fabrication of devices which depend on quantum transport phenomena will likely require the use of metal features in the nanometer linewidth range.
Several alternative techniques have been developed to produce resist masks with more etching resistance. The most commonly employed method involves a two step resist mask production process. A first, relatively thick resist layer with a thickness of about 1000 nanometers (nm) is deposited on the oxide layer. Over this thick resist layer, a second, relatively thin resist layer having a thickness of about 1 nm is deposited. A pattern is developed in the thin resist layer and then both resist layers are selectively removed by reactive ion etching (RIE). However, RIE is a complex process, requiring significant expenditures for capital equipment and operator training In addition, the current linewidth resolution in commercial resist-related lithography is about 0.25 microns due to electron scattering which broadens the developed regions on the resist.
Another method for overcoming the difficulties resulting from the fabrication of smaller and smaller devices is the formation of a metal mask to replace the resist masks discussed above. U.S. Pat. No. 4,578,157 discloses a method of laser induced metal deposition onto a layer of gallium arsenide (GaAs) semiconductor substrate. Metal deposition or metallization is controlled by pulsing a laser beam through a metal bearing solution as the substrate is precisely moved by a computer controlled positioning device. This maskless process again requires substantial outlays for capital equipment. Photolithography also inherently limits the linewidth resolution to a fraction of a micron.
Methods for producing vertical sidewall structures on microcircuit substrates are also disclosed in U.S. Pat. Nos. 4,343,082, 4,432,132, 4,455,738, 4,502,914, 4,784,718, 4,803,181 and 4,886,763. The majority of the disclosed techniques are methods for forming insulating sidewalls using materials such as silicon oxide, silicon nitride, aluminum oxide and silylated organic polymers Sidewalls formed from these materials are used to provide improved electronic devices such as MESFETS and MOSFETS by producing improved self alignment in the device substructures along with reduced resistance. U.S. Pat. No. 4,358,340 discloses a method for fabricating submicron conducting structures by depositing a conducting film on a vertical step, and then thinning the conducting layer until only the film adjacent to the vertical step is left.
Heretofore, commercial lithographic methods of producing structures of less than 0.1 microns linewidth have not been developed.